The present disclosure relates to a semiconductor structure, and particularly to a trench capacitor structure including dual node dielectric layers and methods of manufacturing the same.
Deep trench capacitors are used in a variety of semiconductor chips for high areal capacitance and low device leakage. Typically, a deep trench capacitor provides a capacitance in the range from 4 fF (femto-Farad) to 120 fF. A deep trench capacitor can be employed as a charge storage unit in a dynamic random access memory (DRAM), which can be provided as a stand-alone semiconductor chip, or can be embedded in a system-on-chip (SoC) semiconductor chip. A deep trench capacitor can also be employed in a variety of circuit applications such as a charge pump or a capacitive analog component in a radio-frequency (RF) circuit.
Deep trench capacitors are formed in a semiconductor substrate, which can be a semiconductor-on-insulator (SOI) substrate or a bulk substrate. Other semiconductor devices such as field effect transistors can be formed on the same semiconductor substrate, thereby enabling embedding of deep trench capacitors into a semiconductor chip. Such embedded deep trench capacitors enable various functionality including embedded dynamic access memory (eDRAM) and other embedded electronic components requiring a capacitor.
While deep trench capacitors provide a high capacitance per unit area, scaling of deep trench capacitors is difficult because maintaining the depth of a deep trench becomes more difficult as the lateral dimension of the deep trench are reduced. Thus, the capacitance per unit area of a deep trench capacitor employing a conventional structure has a limit. However, a capacitor structure having a greater capacitance per unit area than currently available would free up more area for other semiconductor devices, and thereby increase the device density in integrated semiconductor circuits.